Programmable logic devices (PLDs) are a well-known type of IC that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
FIG. 1 is a simplified illustration of an exemplary FPGA 100. The FPGA of FIG. 1 includes an array of configurable logic blocks (LBs 101a-101i) and programmable input/output blocks (I/Os 102a-102d). The LBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLs, RAM, and so forth.
A PLD interconnect structure can be complex and highly flexible. For example, Young et al. describe the interconnect structure of an exemplary FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”, which is incorporated herein by reference in its entirety.
FPGA “families” are typically created by including differently-sized arrays of the same logic blocks. For example, the FPGA illustrated in FIG. 1 includes a 3×3 array of LBs. The arrays are typically much larger in actual devices, but a small array is illustrated in FIG. 1, for clarity. An FPGA device family might include, for example, one device with an 8×8 array, one device with an 8×16 array (or two 8×8 arrays), one device with a 16×16 array (or two 8×16 arrays), and so forth. A separate mask set is created for each member of the FPGA family, and each family member has a separate test program, a separate characterization program, separate packaging, and so forth.
Note that the FPGA illustrated in FIG. 1 is similar to other ICs in that the FPGA is surrounded by a “scribe line”, “scribe”, “scribe area”, or “dieseal” 106. A scribe line is an area typically including many of the various processing layers that make up the FPGA die, e.g., the diffusion layers and all of the metal layers. There are no circuit structures in the scribe line, except that relatively small test structures and/or alignment marks can be inserted to assist in the fabrication and test processes. The scribe line is the area in which the die are sawn apart when wafer processing is complete. Therefore, structures located within the scribe line are typically destroyed during the manufacturing process.
FIG. 2 illustrates an exemplary wafer 200 including 37 dice, implementing 37 copies of FPGA 100 from FIG. 1. FIG. 2 also illustrates an exemplary pattern of defects 201 introduced during fabrication. The defects are illustrated as small squares containing an “X”. During the manufacturing process, a wafer is typically tested prior to sawing the wafer into separate dice. Each die that includes a disabling defect is marked with a dot of ink 202. These dice are discarded prior to the packaging step. Note that with the defect pattern illustrated in FIG. 2, 14 dice are discarded, and 23 dice are passed for packaging.
As will be clear from FIG. 2, the larger the size of a die in proportion to the size of the wafer, the greater the chance that the die area will include one or more of the defects. Die sizes are generally increasing as the IC industry evolves. At the same time, the surface density of structures on the die is also increasing as minimum feature sizes are reduced, so each defect is more likely to occur in an area sensitive to such defects. Hence, manufacturing defects are an increasing problem in the manufacture of ICs, including FPGAs and other PLDs.
Therefore, it is desirable to provide methods and structures that increase the yield of die per wafer by minimizing the impact of manufacturing defects.